In semiconductor manufacturing, process corners represent extremes of fabrication parameter variations within which a circuit must function correctly. In other words, a corner is a model that represents the worst case scenario for a particular metric. To obtain the worst case performance, parameters are varied globally (chip to chip) and locally (within chip). Monte Carlo simulation, if appropriately calibrated, is an accurate way to explore circuit performance variations. However, this approach requires intensive computational resources. Fixed process corners are sought to provide coverage on various worst case scenarios (as seen in the Monte Carlo simulation) without invoking the computationally intensive Monte Carlo process. Known solutions are unable to capture the true worst case performance specific to SRAM cells, since existing corners perform a root mean square operation on local and global variation components. Also, existing solutions assume equal contributions from local and global components, which does not represent the true worst case bit on the chip. In addition, prior art process corners do not allow scaling behavior of worst case Iread with respect to local and global sigma settings. Accordingly, each new customer design and/or memory size requirement necessitates a new set of Monte Carlo simulations.
A need therefore exists for more efficient and accurate methodology enabling simulation of true worst case performance for an SRAM and for designing SRAMs without running Monte Carlo simulations.